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SAN3010 APPLICATION NOTE
SINGLE CHIP TELEPHONE INTERFACE FOR KEYBOARD ENTRY VIA uC
1 Scope
This application note describes a simple interface for keyboard entry to the SA253x family via a Microcontroller. It also includes hardware description , flowchart and a software example based on the 80Cxx - family of Microcontrollers.
2 Key Features
* * * * * only 5 outputs and 1 input required from C for handshake to access all keys in the SA253x keyboard matrix universal interface, not restricted to specific Microcontrollers supports both 3V- and 5V- Cs same hardware for all single chip telephones : SA2531/2 same software for all single chip telephones, only key labels must be replaced
Table of Contents
1 SCOPE.............................................................................................................................................................................................................1 2 KEY FEATURES ..............................................................................................................................................................................................1 3 OTHER APPLICABLE DOCUMENTS AND PAPERS ......................................................................................................................................1 4 REVISION STATUS .........................................................................................................................................................................................2 5 GENERAL DESCRIPTION ...............................................................................................................................................................................2 6 HARDWARE CONFIGURATION ......................................................................................................................................................................2 7 APPLICATION SCHEMATIC:...........................................................................................................................................................................2 8 SCANNING TABLE/FLOWCHART...................................................................................................................................................................3 9 SAMPLE SOFTWARE......................................................................................................................................................................................3 10 KEY ENTRY SIGNAL TABLE: .......................................................................................................................................................................4 11 APPENDIX A: APPLICATION SCHEMATIC ..................................................................................................................................................5 12 APPENDIX B: FLOWCHART: ........................................................................................................................................................................6 13 APPENDIX C: SAMPLE SOFTWARE LISTING .............................................................................................................................................7 14 LIABILITY AND COPYRIGHT STATEMENT ................................................................................................................................................13
3 Other applicable documents and papers
1. 2. 3. 4. Data Sheet SA2531, SA2532 Pin-out Comparison SA2531/2 Product Presentation Single Chip Telephone Evolution (Apr. 16, 1996)
SAN3010
PDS038-SA2531/2-003
Rev. B
21-03-00
SAN3010
4 Revision status
SAN3010 Application Note (this document): AN3010 Schematic: AN3010 Sample Software Rev.: A02 Rev.: A01
5 General Description
The interface must be capable of forcing the keyboard rows (hereafter indicated as R1...R4) both low (Vss) and high (VDD) and forcing the keyboard columns (hereafter indicated as C1...C4) to high (VDD). Only one row or column is forced at the same time while the remaining rows/columns must be high ohmic (hereafter indicated as Hi Z). Since only one row/column must be driven at the same time, a decoder (IC5 = 74138) was implemented to save pin count of the C. 3 output ports were used for row/column selection, 1 output port to disable all rows/columns and 1 output port for the 3-state buffer inputs to select forcing high or low . One C pin must be configured as input for handshake. If 9 output + 1 input pins are available from the C (8 row/column selectors, 1 force hi/lo selector , 1 handshake input) , IC5 = 74138 can be omitted. IC3 & 4 (=74HC125) are separately addressable 3-state buffers. A simple discrete NOR gate (Q1,D2,D3,R9..11) is used for synchronization.
6 Hardware configuration
The SA253x Single Chip Telephone can be connected to a C for key entry when the following conditions are met: Supply voltage: The SA253x works at 4V VDD, its high/low input levels are 30/70% VDD. If the C is supplied with >4V a current limiter (serial resistor) must be added to the row/column pins of the SA253x. If the C supply is <4V it must provide adequate high level (> 70%VDD of SA253x = >2.8V) Row driver : 4 Tristate output pins, each separately adjustable as either output (Hi/Lo) or tristate . Only one row is driven at the same time, all other rows/columns are high ohmic. Column driver: Tristate output pins, each separately adjustable as either output (Hi) or tristate. Only one column is driven at the same time, all other rows/columns are high ohmic. Synchronization: The SA253x is intentionally designed for low standby power, so no oscillator is running as long as no key is pressed. All the external row/column driving is done asynchronously. The scanning sequence is synchronized by triggering a rising edge on specific columns (see table 1). Therefore a 1-bit input must be provided for the synchronization.
7 Application schematic:
See also: Appendix A: One solution which only requires 5 output pins and 1 input pin is shown in the attached schematic. A common C (80C51-family) is used. This controller is widely known, so both hardware and software description in this application note should be easily understood which simplifies adaption to any other controller. The rows/columns are driven by 8 separately selectable tristate buffers (e.g. 74HC125). Power supply is 5V, therefore resistors R2...R8 are necessary to provide adaption to the 4V-logic of the SA253x. R1 is always connected by a 5kOhms resistor to prevent collision of two outputs when it initiates the key entry in an unsynchronous state.
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SAN3010 Since only one row/column is forced high or low at the same time the number of C output port pins can be limited by using a 1-of-8 decoder (74HC138). The 3 bits (A,B,C, respectively Port1 pins 0..2) select the appropriate row/column, Port 1.4 disables all outputs. The selected row/column is forced high or low depending on the state of Port1.5 . Port 1.7 is used as input to detect the acknowledge of the SA253x during the scanning phase. Acknowledge is done by the rising edge of either C1,C2,C3 or C4. The detection logic can be simplified by just monitoring C1 and C2, because one of both can always be used for detection (see table 1, ColY). Diode D1 is necessary to prevent collision of two outputs when Port1 is in output mode. Since Port1 of the 80C31 is an open-drain output a diode can be used. For other controllers, using standard I/O, a resistor must be used in place of the diode.
8 Scanning table/flowchart
See also: Appendix B: The interfacing procedure is shown in the attached flowchart, additional information is given below: 1) Key entry can only occur, when the SA253x has been off-hook for >20ms. 2) Internal key scanning of the SA253x is started when any Row (in our case: R1) has been forced low, then the acknowledge by the SA253x is done by moving specific col-pins high. 3) When this Lo/Hi transition is detected by the C the asynchronous timing must be started. 4) SCAN1 and SCAN 2 are the time slots at which a certain row must be forced high (SCAN1) and forced low (SCAN 2 ) , at time slot SCAN3 a certain column must be forced high. The key entry corresponding Row and Column is shown in table 1. Between the SCAN1..3 time slots all rows and columns must be high ohmic (see flowchart). 5) a valid key entry is accepted, when the SCAN1..3 procedure has been repeated 9 times. 6) a certain constant delay must be added between key entries. The only exception is, when memory keys are cascaded. In this special case, entering a subsequent memory key is only accepted, when the previous memory has been fully dialed out.
9 Sample software
See also: Appendix C: Attached is a sample software program, written in 8051 Assembler language which incorporates all the necessary timing and correct row/column selection. The only entry is to load the accumulator with a key code and then make a subroutine call. See Table 1 for appropriate key codes when using either SA2531-2 The assembler command lines are well described, so it should be easily understood. Again, adaption to other controllers based upon this software should be no problem. Care must be taken when using a different system clock speed. In this case the delay blocks must be recalculated based on the number of machine cycles used.
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10 Key entry signal table:
Keycode in S/W example Key - ID. Key - ID.
SA2531 Mute 1 2 3 4 5 6 7 8 9 0 * # Pause R R2 LNR VOL VOL + VOL Enter M5 M6 M7 M8 M9 M10 M1 M2 M3 M4 Mem
SA2532 Mute 1 2 3 4 5 6 7 8 9 0 * # Pause R R2 LNR
SCAN 1 SCAN 2 Row X Row X force Hi force Lo
SCAN 3 Col X force Hi
Synchronization on Col Y:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R1 R1 R1 R1 R2 R2 R2 R2 R3 R3 R3 R3 R4 R4 R4 R4 none none none none none none none none none none none none none none none none
R1 R1 R1 R1 R2 R2 R2 R2 R3 R3 R3 R3 R4 R4 R4 R4 R1 R1 R1 R1 R2 R2 R2 R2 R3 R3 R3 R3 R4 R4 R4 R4
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3
Table 1: key entry lookup table
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11 Appendix A: Application Schematic
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12 Appendix B: Flowchart:
Flowchart for Microcontroller interface to AS253x single-chip-telephone Notes: RowX,ColX,ColY: see table1 1 tclk= 256/3.58MHz = 71.5s all timings: Tol.:+-30s
Start
delay5
wait >20ms after AS253x off-hook to ensure correct start-up wait 4.5 tclk= 321s and force ColX high all other rows/cols= Hi Z =SCAN3
Key_in delay6
Loop=0 wait 1.5 tclk=107.25s and disable all rows/cols= Hi Z
Row1 force low all other rows/cols=Hi Z
sync
Loop= Loop+1
Col Y=high ?
No
Loop = 9 ?
No
delay1
Yes Yes
wait 1 tclk=71.5s and force RowX high all other rows/cols= Hi Z =SCAN1
delay7
wait 24*9 tclk=15.5ms
delay2
wait 1.5 tclk=107.25s and disable all rows/cols= Hi Z another key entry?
Yes
delay3
wait 4.5 tclk=321s and force RowY low all other rows/cols= Hi Z =SCAN2
No
end
delay4
wait 4.5 tclk=321s and disable all rows/cols= Hi Z
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13 Appendix C: Sample Software listing
MCS-51 MACRO ASSEMBLER 09/09/96 PAGE 1 LOC OBJ LINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 0000 41 0001 42 0002 43 0003 44 0004 45 0005 46 0006 47 0007 48 0090 49 0080 50 KEY SOURCE ; (c) Austria Mikro Systeme International AG AMS ; J.Janisch / telecom applications ; Program name: KEY.ASM ; Version: A01 ; Date: 1996-09-09 ; Author: J.Janisch / Telecom Applications ; ; User program for 8051 interface to SA253x for key entry via ; microcontroller ; Application Note AN3010 ; Program code is at Address 4000 HEX ; ; Reference for calculations: ; Clock Frequency of Microcontroller (80C31) = 11.0592 MHz ; --> 1 machine cycle = 12 clock cycles = 1.085 us ; ; Decoder Logic: ; Port1: ; P1.7 : active low input; detects rising edge of C1 OR C2 ; should be set high by any output command to port 1 ; P1.6 : not used ; P1.5 : not used ; P1.4 : forces selected row/column high or low ; P1.3 : when high, disables all rows/columns (high Z) ; P1.2 : row / column selector MSB ; P1.1 : row / column selector ; P1.0 : row / column selector LSB ; ; P1.2 P1.1 P1.0 select: ; 0 0 0 row 1 ; 0 0 1 row 2 ; 0 1 0 row 3 ; 0 1 1 row 4 ; 1 0 0 column 1 ; 1 0 1 column 2 ; 1 1 0 column 3 ; 1 1 1 column 4 ;
Row1 Row2 Row3 Row4 Col1 Col2 Col3 Col4 ForceHi ForceLo
equ equ equ equ equ equ equ equ equ equ
0 1 2 3 4 5 6 7 90H 80H
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PAGE 2 LOC OBJ 0088
4000 4000 758160 4003 00
4004 740A 4006 12400B 4009 80FE
400B 12405C
400E 4010 4012 4014 4017
7B00 7480 F590 3097FD 2097FD
401A 791F 401C D9FE 401E 7490 4020 4D 4021 F590
4023 7930 4025 D9FE 4027 7488
LINE 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
SOURCE Disable equ
88H
; ############################################################# ; Main program: load Accumulator with key code (see below) and ; call subroutine "Key_In" ; set start address of program ; set stack pointer HS_OK: ; make sure that at this point ; the SA253x has been off-hook ; for >20ms Ld_Key: mov a,#10 ; load keycode, here key "0" Call Key_in ; execute keystroke jmp $ ; end of main program, exit at ; this point or continue with ; next key entry ; rem.: add additional delay when ; cascading memories (s. Delay7:) ; ############################################################# ; ************************************************************* ; Subroutine Key_in ; ************************************************************* ; this subroutine executes a key entry to the SA253x ; the corresponding key code(0...31) must be loaded in the accu ; see table at label:"scantbl" for key codes ; affected Registers: ; A,B,R1,R2,R3,R5,R6,R7,DPTR Org mov NOP 04000H SP,#060H
Key_in: call
getScTb
; preload Reg5..7 with ; Row X: variable in ; Row Y: variable in ; Col X: variable in ; clear loop counter ; force R1 low
scan table Reg5 Reg6 Reg7
Exe_Key:mov mov mov sync: jnb jb
R3,#0 a,#ForceLO P1,A P1.7, $ P1.7, $
; make sure, C1= C2 = low ; wait for rising edge C1 or C2 ; = trigger for asynch. timing
;- Delay 1:wait 71.5 us = 66 machine cycles and force RowX high delay1: mov R1,#31 ; 1 cycle djnz R1,$ ; 2 cycles; #Loops=(66-4)/2 =31 SCAN1: mov orl mov A,#ForceHi A,R5 P1,A ; 1 cycle ; 1 cycle ; 1 cycle
;-------------------------------------------------------------;Delay2:wait 107.25us= 99 machine cycles +disable all rows/cols delay2: mov R1,#48 ; 1 cycle djnz R1,$ ; 2 cycles; #Loops =(99-3)/2 = 48 mov A,#Disable ; 1 cycle
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PAGE 3 LOC OBJ 4029 F590
402B 7991 402D D9FE 402F 4030 4032 4033 00 7480 4E F590
4035 4037 4039 403B
7992 D9FE 7488 F590
403D 7991 403F D9FE 4041 4042 4044 4045 00 7490 4F F590
4047 4049 404B 404D
7930 D9FE 7488 F590
404F 0B 4050 BB09C1
4053 7900 4055 7A1C
LINE 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
SOURCE mov P1,A ; 1 cycle
;-------------------------------------------------------------;-- Delay 3:wait 321 us = 295 machine cycles and force RowY low delay3: mov R1,#145 ; 1 cycle djnz R1,$ ; 2 cycles;#Loops=(295-5)/2=145 SCAN2: NOP mov orl mov ; ; ; ; 1 1 1 1 cycle cycle cycle cycle
A,#ForceLO A,R6 P1,A
;-------------------------------------------------------------;Delay 4: wait 321us= 295 machine cycles +disable all rows/cols delay4: mov R1,#146 ; 1 cycle djnz R1,$ ; 2 cycles;#Loops=(295-3)/2=146 mov A,#Disable ; 1 cycle mov P1,A ; 1 cycle ;-------------------------------------------------------------;--- Delay 5:wait 321 us = 295 machine cycles + force ColX high delay5: mov R1,#145 ; 1 cycle djnz R1,$ ; 2 cycles;#Loops=(295-5)/2=145 NOP ; 1 cycle mov A,#ForceHi ; 1 cycle orl A,R7 ; 1 cycle mov P1,A ; 1 cycle ;-------------------------------------------------------------;Delay 6:wait 107.25us=99 machine cycles +disable all rows/cols delay6: mov R1,#48 ; 1 cycle djnz R1,$ ; 2 cycles;#Loops=(99-3)/2 = 48 mov A,#Disable ; 1 cycle mov P1,A ; 1 cycle ;-------------------------------------------------------------inc R3 ; increment loop counter cjne R3,#9,Sync ; repeat loop 9 times SCAN3:
;----- Delay 7: wait >15444 us = 14233 machine cycles before ;----next key entry ;----- Remark: when cascading memory keys (M1...M10, Mem) ;----- dialling of a subsequent stored number is only accepted ;----- when the previous number has been fully dialled out. ;----- Example1: key entry is "M1","M2" ;----M2 is only detected when M1 has completed dialing ;----its stored number, a delay has to be added between ;----key entries ;----- Example2: key entry is "M1","0" ;---numbers are stored in FIFO ,so they can be entered ;----immediately after a Memory entry, no additional ;----delay necessary delay7: mov R1,#0 ; mov R2,#28
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PAGE 4 LOC OBJ 4057 D9FE 4059 DAFC
405B 22
405C 405F 4062 4063
904074 75F003 A4 F5F0
4065 93 4066 FD 4067 4069 406A 406C 406D 406E 4070 4071 4072 E5F0 04 F5F0 93 FE E5F0 04 93 FF
4073 22
4074 4075 4076 4077 4078 4079 407A 407B 407C 407D 407E 407F 4080 4081 4082 4083
00 00 04 00 00 05 00 00 06 00 00 07 01 01 04 01
LINE 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
SOURCE Del7a:
djnz djnz
R1,$ R2,Del7a
; =256*2 machine cycles ; =2 machine cycles ; 28*(256*2+2)=14392mc's=15.6ms ; return from subroutine
ret
;************************************************************** ; Subroutine GetScTb ;************************************************************** ; this subroutine loads the Reg5..Reg7 registers according to ; the keycode passed by the accumulator contents. ; valid keycodes are 0.....31 (dec) = 0....1F (Hex)
GetScTb:mov mov mul mov movc mov mov inc mov movc mov mov inc movc mov ret
dptr,#Scantbl B,#3 AB B,A A,@A+DPTR R5,A A,B A B,A A,@A+DPTR R6,A A,B A A,@A+DPTR R7,A
; calculate offset Address: ; scantable startaddress ; + (keycode *3) ; save offset address ; get scan table: Row X ; RowX
; ; ; ;
get next code save get scan table: Row X RowY
; get next code ; get scan table: Row X ; ColX
; Scan table: the three constants indicate the rows/columns ; to be driven in the SCAN1....SCAN3 phase ; Scantbl:db Row1,Row1,Col1 ; key "Pgm/Mt, keycode= 0
201
db
Row1,Row1,Col2
;
key "1"
, keycode= 1
202
db
Row1,Row1,Col3
;
key "2"
, keycode= 2
203
db
Row1,Row1,Col4
;
key "3"
, keycode= 3
204
db
Row2,Row2,Col1
;
key "4"
, keycode= 4
205
db
Row2,Row2,Col2
;
key "5"
, keycode= 5
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PAGE LOC 4084 4085 4086 4087 4088 4089 408A 408B 408C 408D 408E 408F 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 409A 409B 409C 409D 409E 409F 40A0 40A1 40A2 40A3 40A4 40A5 40A6 40A7 40A8 40A9 40AA 40AB 40AC 40AD 40AE 40AF 40B0 40B1 40B2 40B3 40B4 40B5 40B6 40B7 40B8 40B9 40BA 5 OBJ 01 05 01 01 06 01 01 07 02 02 04 02 02 05 02 02 06 02 02 07 03 03 04 03 03 05 03 03 06 03 03 07 88 00 04 88 00 05 88 00 06 88 00 07 88 01 04 88 01 05 88 01 06 88 01
LINE
SOURCE
206
db
Row2,Row2,Col3
;
key "6"
, keycode= 6
207
db
Row2,Row2,Col4
;
key "7"
, keycode= 7
208
db
Row3,Row3,Col1
;
key "8"
, keycode= 8
209
db
Row3,Row3,Col2
;
key "9"
, keycode= 9
210
db
Row3,Row3,Col3
;
key "0"
, keycode= 10
211
db
Row3,Row3,Col4
;
key "*"
, keycode= 11
212
db
Row4,Row4,Col1
;
key "#"
, keycode= 12
213
db
Row4,Row4,Col2
;
key "PS,R1", keycode= 13
214
db
Row4,Row4,Col3
;
key "R,R2" , keycode= 14
215
db
Row4,Row4,Col4
;
key "R2,R3 , keycode= 15
216
db
disable,Row1,Col1 ;
key "LNR"
, keycode= 16
217
db
disable,Row1,Col2 ;
key "Vol"
, keycode= 17
218
db
disable,Row1,Col3 ;
key "Vol+" , keycode= 18
219
db
disable,Row1,Col4 ;
key "Vol-" , keycode= 19
220
db
disable,Row2,Col1 ;
keycode= 20
221
db
disable,Row2,Col2 ;
keycode= 21
222
db
disable,Row2,Col3 ;
keycode= 22
223
db
disable,Row2,Col4 ;
keycode= 23
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PAGE LOC 40BB 40BC 40BD 40BE 40BF 40C0 40C1 40C2 40C3 40C4 40C5 40C6 40C7 40C8 40C9 40CA 40CB 40CC 40CD 40CE 40CF 40D0 40D1 40D2 40D3 6 OBJ 07 88 02 04 88 02 05 88 02 06 88 02 07 88 03 04 88 03 05 88 03 06 88 03 07
LINE 224
SOURCE db disable,Row3,Col1 ; keycode= 24
225
db
disable,Row3,Col2 ;
keycode= 25
226
db
disable,Row3,Col3 ;
keycode= 26
227
db
disable,Row3,Col4 ;
keycode= 27
228
db
disable,Row4,Col1 ;
keycode= 28
229
db
disable,Row4,Col2 ;
keycode= 29
230
db
disable,Row4,Col3 ;
keycode= 30
231
db
disable,Row4,Col4 ;
keycode= 31
232 233 234 REGISTER BANK(S) USED: 0
end
ASSEMBLY COMPLETE, NO ERRORS FOUND
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14 Liability and Copyright Statement
Disclaimer: The information contained in this document is confidential and proprietary to South African Micro-Electronic Systems (Pty) Ltd ("SAMES") and may not be copied or disclosed to a third party, in whole or in part, without the express written consent of SAMES. The information contained herein is current as of the date of publication; however, delivery of this document shall not under any circumstances create any implication that the information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to inform any recipient of this document of any changes in the information contained herein, and SAMES expressly reserves the right to make changes in such information, without notification,even if such changes would render information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any circuit designed by reference to the information contained herein, will function without errors and as intended by the designer.
South African Micro-Electronic Systems (Pty) Ltd
P O Box 15888, Lynn East, 0039 Republic of South Africa, 33 Eland Street, Koedoespoort Industrial Area, Pretoria, Republic of South Africa
Tel: Fax:
012 333-6021 012 333-3158
Tel: Fax:
Int +27 12 333-6021 Int +27 12 333-3158
Web Site : http://www.sames.co.za
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